Resistor with doped regions and semiconductor devices having the same

ABSTRACT

A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No. 17/371,494 filed on Jul. 9, 2021, which claim priority from U.S. patent Ser. No. 16/784,788 filed on Feb. 7, 2020, and Korean Patent Application No. 10-2019-0088382, filed on Jul. 22, 2019, the disclosures of each of these applications are incorporated herein by reference in their entirety.

BACKGROUND 1. Field

Devices consistent with example embodiments relate to a resistor with a doped region and a semiconductor device having the same.

2. Description of Related Art

Electronic devices may include one or more semiconductor devices components. Applications that use semiconductor devices include smart phones, tablet computers, and cameras. A transistor is an example of a semiconductor device, and is used to amplify or modify electronic signals.

Demand for smaller electronic devices is increasing. As a result, demand for smaller semiconductor devices that do not compromise performance transistors is also increasing. However, reducing the size of a semiconductor device such as transistor can cause short channel effects such as drain-induced barrier lowering, velocity saturation, and hot carrier degradation. Therefore, there is a need in the art to provide for semiconductor devices that reduce the likelihood of short channel effects in a circuit.

SUMMARY

Example embodiments of inventive concepts are directed to providing a semiconductor device with a resistor in a surrounding gate structure.

According to some example embodiments, a resistor may include a first active region and a second active region each extending in a first horizontal direction, the first active region and the second active region being spaced apart from each other along the first horizontal direction; a device isolation layer contacting the first active region and the second active region; a buried insulating layer disposed between the first active region and the second active region; an N well region formed in a substrate, the N well region surrounding the first active region, the second active region, the device isolation layer and the buried insulating layer; a plurality of channel layers stacked on the first active region and the second active region, the plurality of channel layers being spaced apart from each other in a vertical direction; first gate electrodes surrounding the plurality of the channel layers, the first gate electrodes extending along a second horizontal direction intersecting with the first horizontal direction; a doped region comprising a first doped region and a second doped region each disposed on side surfaces of the first gate electrodes above the first active region and the second active region, respectively, in the vertical direction, the first doped region and the second doped region in contact with the N well region and including n type impurities; a plurality of contact plugs in contact with upper surfaces of the first doped region and the second doped region.

According to some example embodiments, a semiconductor device may include a substrate comprising a resistor region and a transistor region; an N well region disposed on the resistor region; a first active region and a second active region each extending in a first horizontal direction, the first active region and the second active region being spaced apart from each other along the first horizontal direction; a first device isolation layer contacting the first active region and the second active region; a buried insulating layer disposed between the first active region and the second active region; a plurality of channel layers stacked on the first active region and the second active region, the plurality of channel layers being spaced apart from each other in a vertical direction; gate electrodes surrounding the plurality of the first channel layers on at least two opposite sides, the gate electrodes extending along a second horizontal direction intersecting with the first horizontal direction; a first doped region and a second doped region each disposed on side surfaces of the gate electrodes on the first active region and the second active region, the first doped region and the second doped region in contact with the N well region and including n impurities; a plurality of contact plugs in contact with upper surfaces of the first doped region and the second doped region.

According to some example embodiments, a resistor may include an active region comprising a first active region and a second active region each extending in a first horizontal direction, the first active region and the second active region being spaced apart from each other along the first horizontal direction; a device isolation layer contacting the first active region and the second active region; a buried insulating layer disposed between the first active region and the second active region and formed deeper than the device isolation layer; an N well region formed in a substrate; the N well region surrounding the first region, the second active region, the device isolation layer and the buried insulating layer; a plurality of channel layers stacked on the first active region and the second active region, the plurality of channel layers being spaced apart from each other in a vertical direction; gate electrodes surrounding the plurality of the channel layers on at least two opposite sides, the gate electrodes extending along a second horizontal direction intersecting with the first horizontal direction; a doped region comprising a first doped region and a second doped region each disposed on side surfaces of the gate electrodes on the first active region and the second active region, the first doped region and the second doped region in contact with the N well region and including n impurities; inner spacers in contact with a side surface of the doped region and disposed on lower surfaces of the plurality of channel layers; gate spacers disposed on the active region and the plurality of the channel layers, the gate spacers covering the side surfaces of the gate spacers; an interlayer insulating layer covering the device isolation layer, the buried insulating layer, the gate spacers, the first doped region, and the second doped region; a plurality of contact plugs in contact with the first doped region and the second doped region, the plurality of contact plugs penetrating the interlayer insulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features, and advantages of inventive concepts will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the accompanying drawings, in which:

FIG. 1 is a layout of a semiconductor device according to an example embodiment of inventive concepts.

FIGS. 2A-2D are vertical cross-sectional views of the semiconductor device of FIG. 1 , taken along line I-I′, and IV-IV′, respectively.

FIG. 3 and FIG. 4 are vertical cross-sectional views of the resistor according to an example embodiment of inventive concepts.

FIGS. 5A-14C are vertical cross-sectional views illustrating in a process order of a method of manufacturing a semiconductor device according to an example embodiment of inventive concepts.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Embodiments of the present disclosure include semiconductor devices that reduce the likelihood of short channel effects in a circuit. For example, a resistor is described that includes a well region divided into two parts by a buried insulating layer and a semiconductor layer epitaxially grown from a silicon substrate. The semiconductor layer may include materials of the same conductivity type as the N well region.

According to an example embodiment, the resistor may be formed simultaneously with a Multi-Bridge Channel Field Effect Transistor (MBCFET). In this case, the multi-bridge channel structure is also applied to the resistor the manufacturing stage of the MBCFET. Additionally, in MBCFET, the width of the channel can be arbitrarily changed. Therefore, a resistor having different resistances can be implemented according to the width of the channel.

FIG. 1 is a layout of a semiconductor device according to an example embodiment of inventive concepts. FIGS. 2A-2D are vertical cross-sectional views of the semiconductor device of FIG. 1 , taken along line I-I′, and IV-IV′, respectively.

Referring to FIG. 1 and FIGS. 2A-2D, a semiconductor device 100 may include a substrate 102, a channel layer 114, a device isolation layer 120, a buried insulating layer 122, a gate electrode 134, a doped region 150, a source/drain region 152, and an interlayer insulating layer 160. The semiconductor device 100 may further include a contact plug 180, a via V, and interconnects L1, L2, L3, L4, L5, L6, and L.

The semiconductor device 100 may include a resistor region R1 and a transistor region R2. The resistor region R1 may include a resistor 106, and the transistor region R2 may include a transistor 108. The resistor 106 includes a first active region 104 a, a second active region 104 b, an N well region NW below the buried insulating layer 122, a first doped region 150 a, and a second doped region 150 b. The transistor 108 may include a plurality of channel layers 114, a source/drain region 152, and a gate electrode 134.

Substrate 102 may include a semiconductor material. For example, the substrate 102 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a silicon on insulator (SOI) substrate. In an example embodiment, the substrate 102 may be a P-type semiconductor substrate and may include an N well region NW on top of the resistor region R1 of the substrate 102. Substrate 102 may include device isolation layer 120 defining active region 104. For example, a portion of the substrate 102 located between portions of the device isolation layer 120 may correspond to an active region 104. A plurality of active regions 104 may extend in the first horizontal direction D1 and may be spaced apart from each other along the second horizontal direction D2. The plurality of active regions 104 may include a first active region 104 a and a second active region 104 b disposed at opposite sides of the buried insulating layer 122.

The plurality of channel layers 114 may be stacked spaced apart from each other in a vertical direction on the substrate 102. In FIG. 2B, the channel layer 114 in the form of a nanosheet with a rectangular cross-section is illustrated but is not limited thereto. In an example embodiment, the cross-section of the channel layer 114 may be circular or elliptical. Each channel layer 114 may have a predetermined length along the first horizontal direction D1 and the second horizontal direction D2. In an example embodiment, the channel layer 114 may include one or more of a group IV semiconductor such as Si, Ge, SiGe or a group III-V compound semiconductor such as InGaAs, InAs, GaSb, InSb, or the like.

The device isolation layer 120 may fill the inside of a first trench T1 formed on the substrate 102. The device isolation layer 120 may be disposed between the plurality of active regions 104 and may extend in the first horizontal direction D1. The buried insulating layer 122 may fill the inside of a second trench T2 formed on the substrate 102. The buried insulating layer 122 may be disposed in the middle of the plurality of active regions 104. The second trench T2 may be formed deeper than the first trench T1. The buried insulating layer 122 may not penetrate the N well region NW. For example, the N well region NW may surround a bottom surface of the buried insulating layer 122. A top surface of the active region 104 may be located at a similar level as top surfaces of the device isolation layer 120 and the buried insulating layer 122, respectively. In an example embodiment, device isolation layer 120 and buried insulating layer 122 may comprise silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant (low-K) dielectric material.

A gate dielectric layer 132 and the gate electrode 134 may surround the channel layer 114. The gate dielectric layer 132 may extend in the second horizontal direction D2 and cover the top surfaces of the active region 104 and the device isolation layer 120. Additionally, the gate dielectric layer 132 may surround the surface of the channel layer 114. The gate electrode 134 may extend in the second horizontal direction D2 and may cover the channel layer 114 and the gate dielectric layer 132. The gate dielectric layer 132 may include a material with a high dielectric constant (high-k) such as hafnium oxide, hafnium oxy-nitride, or the like. The gate electrode 134 may include aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys or combinations thereof In an example embodiment, the gate electrode 134 may comprise tungsten.

Gate spacers 140 may be disposed outside the gate electrode 134. For example, the gate spacers 140 may be disposed to face each other with the gate electrode 134 interposed therebetween. The gate spacers 140 may extend in the second horizontal direction D2. The gate spacer 140 may be formed of one or more layers.

Inner spacers 142 may be disposed at both sides of the gate electrode 134 along the second horizontal direction D2. The inner spacers 142 may be disposed on a bottom surface of each channel layer 114 and may contact outer surfaces of the doped region 150 and the source/drain region 152, respectively. The inner spacers 142 may electrically separate the gate electrode 134 from the doped region 150 or the source/drain region 152. In an example embodiment, the inner spacers 142 may comprise a silicon nitride material.

The doped region 150 may be disposed on the active region 104 of the resistor region R1 and may be disposed on the side of the gate electrode 134. A plurality of doped regions 150 may include the first doped region 150 a and the second doped region 150 b disposed at both sides of the buried insulating layer 122. The doped region 150 may be in contact with the N well region NW. The doped region 150 may be doped with the same type of conductive material as the N well region NW. For example, the doped region 150 may include n-type impurities. In an example embodiment, the doped region 150 may include an n-type impurity with a higher concentration than the N well region NW. Since the doped region 150 is doped with the same type of conductive material as the N well region NW, the resistor 106 may not function as a transistor. The first doped region 150 a may be electrically connected to the second doped region 150 b through first active region 104 a, the N well region NW, and the second active region 104 b.

The source/drain region 152 may be disposed on the active region 104 of the transistor region R2 and may be disposed on a side of the gate electrode 134. Adjacent source/drain regions 152 may be electrically connected through each channel layer 114. In an example embodiment, the source/drain regions 152 may include n-type impurities.

The interlayer insulating layer 160 may cover the device isolation layer 120, the buried insulating layer 122, the gate spacer 140, the doped region 150, and the source/drain region 152. The interlayer insulating layer 160 may include silicon oxide, silicon nitride, silicon oxynitride, or a low-K dielectric material and may be composed of one or more layers. The low-K dielectric materials may include, for example, Undoped Silica Glass (USG), Borosilica Glass (BSG), PhosphoSilica Glass (PSG), BoroPhosphoSilica Glass (BPSG), Plasma Enhanced Tetra Ethyl Ortho Silicate (PETOS), Fluoride Silicate Glass (FSG) (High Density Plasma) oxide or a combination thereof.

The capping layer 170 may be disposed on the interlayer insulating layer 160. The capping layer 170 may cover top surfaces of the gate electrode 134, the gate spacer 140, and the interlayer insulating layer 160. The capping layer 170 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The contact plug 180 may vertically penetrate the interlayer insulating layer 160 and the capping layer 170 to contact the top surface of the doped region 150 and the source/drain region 152. The contact plug 180 may extend in the second horizontal direction D2 and may have a bar shape. Additionally, the contact plug 180 may be electrically connected to the doped region 150 or the source/drain region 152. A silicide layer 182 may be further disposed below the contact plug 180. Additionally, the silicide layer 182 may be disposed between the doped region 150 and the contact plug 180 and between the source/drain region 152 and the contact plug 180. Although not shown, a diffusion barrier layer surrounding side and bottom surfaces of the contact plug 180 may be disposed. The contact plug 180 may include W, Co, Cu, Al, Ti, Ta, TiN, TaN, or a combination thereof. The silicide layer 182 may include a material in which a silicon material is applied to a portion of the contact plug 180.

A contact insulating layer 184 may be disposed on the capping layer 170. The via V and the interconnects L1, L2, L3, L4, L5, L6, and L may pass through the contact insulating layer 184. The via V may electrically connect the contact plug 180 and the interconnects L1, L2, L3, L4, L5, L6, and L. A plurality of vias V may be connected to a contact plug 180 in the second horizontal direction D2. Each contact plug 180 may be connected to the interconnects L1, L2, L3, L4, L5, and L6 through the vias V The interconnects L1, L2, and L3 may be electrically connected to each other. The interconnects L4, L5, and L6 may be electrically connected to each other. In an example embodiment, the interconnects L1, L2, L3 and the interconnects L4, L5, L6 may be integrated with each other. The contact insulating layer 184 may include a silicon oxide material. The vias V and the interconnects L1, L2, L3, L4, L5, L6, and L may include W, Co, Cu, Al, or a combination thereof.

As shown in FIG. 1 and FIGS. 2A-2D, the semiconductor device 100 of the present disclosure may implement the resistor 106 in a surrounding gate structure with the channel layer 114 in the form of a nanosheet. Unlike the finFET device, the transistor with the channel layer 114 in the form of a nanosheet may arbitrarily change the width of the channel layer 114. For example, a width of the second horizontal direction D2 of the channel layer 114 shown in FIG. 2B may be arbitrarily changed, and a width of the second horizontal direction D2 of the doped region 150 may also be changed. Therefore, the resistor 106 with various resistances can be implemented.

FIG. 3 and FIG. 4 are vertical cross-sectional views of the resistor according to an example embodiment of inventive concepts. FIG. 3 and FIG. 4 are vertical cross-sectional views corresponding to line I-I′ of the resistor region of FIG. 1 .

Referring to FIG. 3 , a semiconductor device 200 may include a buried insulating layer 222 disposed between the first active region 104 a and the second active region 104 b. The buried insulating layer 222 may fill the inside of the second trench T2 formed on the substrate 102. In an example embodiment, a depth of the second trench T2 may be substantially the same as a depth of the first trench T1. The buried insulating layer 222 may include the same material as the device isolation layer 120. In an example embodiment, the device isolation layer 120 and the buried insulating layer 222 may be shallow trench isolation (STI).

Referring to FIG. 4 , a semiconductor device 300 may include a gate dielectric layer 332, a gate electrode 334, and a gate spacer 340. The gate spacer 340 may be on the buried insulating layer 122. The gate electrode 334 and the gate spacer 340 may be disposed in parallel with the gate electrode 134. The gate dielectric layer 332 may cover side and bottom surfaces of the gate electrode 334. Additionally, the gate spacer 340 may cover the side of the gate electrode 334. The gate electrode 334 may be electrically insulated from the N well region NW. In FIG. 4 , gate electrode 334 is disposed on the buried insulating layer 122 but is not limited thereto. In an example embodiment, a plurality of gate electrodes 334 may be disposed in parallel with the gate electrode 134 on the buried insulating layer 122. Additionally, although the gate dielectric layer 332 and the gate electrode 334 are disposed inside the gate spacer 340 in FIG. 4 , the present disclosure is not limited thereto. In an example embodiment, a dummy gate structure 130D, which will be described later, may be disposed inside the gate spacer 140.

FIGS. 5A-14C are vertical cross-sectional views illustrating in a process order of a method of manufacturing a semiconductor device according to an example embodiment of inventive concepts. FIGS. 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, and 14A are vertical cross-sectional views corresponding to lines I-I′ of the resistor region R1 of FIG. 1 , respectively. FIGS. 5B, 6B, 7B, 8B, 12B, 13B, and 14B are vertical cross-sectional views corresponding to the line II-II′ of the resistor region R1 of FIG. 1 , respectively. FIGS. 5C, 6C, 7C, 8C, 9B, 11B, and 12C are vertical sectional views corresponding to line of the resistor region R1 of FIG. 1 , respectively. FIGS. 5D, 6D, 7D, 8D, 9C, 10B, 11C, 12D, 13C, and 14C are vertical cross-sectional views corresponding to line IV-IV′ of the transistor region R2 of FIG. 1 , respectively.

Referring to FIGS. 5A-5D, a stack 110 may be disposed on a substrate 102. The stack 110 may include a plurality of alternately stacked sacrificial layers 112 and channel layers 114. In an example embodiment, the substrate 102 may be a P-type semiconductor substrate and may include an N well region NW on top of a resistor region R1 of the substrate 102. In an example embodiment, the channel layer 114 may include the same material as the substrate 102. The sacrificial layer 112 may be a different material as channel layer 114. For example, the sacrificial layer 112 may include SiGe, and the channel layer 114 may include Si.

Referring to FIGS. 6A-6D, a device isolation layer 120 may be formed. A mask pattern M may be disposed on the stack 110. The mask pattern M may include silicon nitride, polysilicon, spin-on hardmask material, or a combination thereof.

An upper portion of the substrate 102, the sacrificial layer 112, and the channel layer 114 may be partially removed along the mask pattern M to form a first trench T1. The device isolation layer 120 may be formed by filling an insulating material in the first trench T1. The device isolation layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, or a low-K dielectric material. An active region 104 of the substrate 102 may be defined by the device isolation layer 120. The active region 104 may extend in the first horizontal direction D1 and may protrude from the substrate 102. The plurality of active regions 104 may be spaced apart from each other along the second horizontal direction D2.

Referring to FIGS. 7A-7D, a buried insulating layer 122 may be formed to fill the inside of the second trench T2. The upper portion of the substrate 102, the sacrificial layer 112, and the channel layer 114 may be partially removed to form a second trench T2. In an example embodiment, the buried insulating layer 122 may be formed deeper than the device isolation layer 120. The buried insulating layer 122 may be disposed in the middle of the active region 104. The buried insulating layer 122 may divide the active region 104 into a first active region 104 a and a second active region 104 b. The buried insulating layer 122 may include the same material as the device isolation layer 120. An upper portion of the device isolation layer 120 and the buried insulating layer 122 may be partially etched to expose the sacrificial layer 112 and the channel layer 114.

Referring to FIGS. 8A-8D, a dummy gate structure 130D and a gate spacer 140 may be formed on the stack 110. The dummy gate structure 130D may extend in the second horizontal direction D2 across the active regions 104. The dummy gate structure 130D may include a dummy gate insulating layer 132D, a dummy gate electrode 134D, and a dummy capping layer 136D that are stacked sequentially. The gate spacer 140 may cover side surfaces of the dummy gate structure 130D and may be formed of one or more layers. The gate spacer 140 may be formed by anisotropic etching after depositing an insulating material on the dummy gate structure 130D.

The dummy gate insulating layer 132D may include silicon oxide and may be formed by a method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The dummy gate electrode 134D may include polysilicon. The dummy capping layer 136D may include silicon nitride, silicon oxynitride, or a combination thereof. The gate spacer 140 may include silicon nitride, silicon oxynitride, or a combination thereof.

Referring to FIGS. 9A-9C, the sacrificial layer 112 and the channel layer 114 may be removed. The sacrificial layer 112 and the channel layer 114 are not covered by the dummy gate structure 130D. Additionally, the sacrificial layer 112 and the channel layer 114 may be anisotropically etched using the gate spacer 140 as an etching mask. The etching process may expose the active region 104. In an example embodiment, a recess may be formed on top of the active region 104.

Referring to FIG. 10A and FIG. 10B, an inner spacer 142 may be formed in the space where the sacrificial layer 112 is removed after etching a portion of side surfaces of the sacrificial layer 112. For example, an anisotropic etching process may be performed after forming a recess on the side of the sacrificial layer 112 and depositing an insulating material on the recess. The channel layers 114 may not be etched when forming of the inner spacers 142.

The inner spacers 142 may be formed on side surfaces of the sacrificial layer 112. Additionally, the inner spacers 142 may be disposed between the plurality of channel layers 114 and between the channel layers 114 and the active region 104. An outer surface of the inner spacer 142 may be coplanar with an outer surface of the channel layer 114. The inner spacers 142 may include a silicon nitride material.

Referring to FIGS. 11A-11C, a doped region 150 may be formed on the side of the dummy gate structure 130D in the resistor region R1. Additionally, a source/drain region 152 may be formed on the side of the dummy gate structure 130D in the transistor region R2.

The doped region 150 and the source/drain region 152 may be formed on the active region 104 along the second horizontal direction D2. The doped region 150 and the source/drain region 152 may be formed by a selective epitaxial growth (SEG) process. Adjacent doped regions 150 may be integrated and adjacent source/drain regions 152 may be integrated. Doped region 150 and source/drain region 152 may each be doped with appropriate ions. In an example embodiment, the doped region 150 and the source/drain region 152 may be doped with n-type impurities. Phosphorus (P), arsenic (As), or the like may be used as the n-type impurities.

Referring to FIGS. 12A-12D, an interlayer insulating layer 160 may be formed and may cover the device isolation layer 120, the buried insulating layer 122, side surface of the gate spacer 140, the doped region 150, and the source/drain region 152. The interlayer insulating layer 160 may fill a space between the doped region 150 and the device isolation layer 120 and between the source/drain region 152 and the device isolation layer 120. The interlayer insulating layer 160 may include silicon oxide, silicon nitride, silicon oxynitride, or a low-K dielectric material. After the interlayer insulating layer 160 is formed, the dummy capping layer 136D may be removed by the planarization process, and a top surface of the dummy gate electrode 134D may be exposed.

Referring to FIGS. 13A-13C, the dummy gate structure 130D may be removed. The exposed sacrificial layer 112 may be removed by a wet etching process after removing the dummy gate electrode 134D and the dummy gate insulating layer 132D. The gate spacer 140 and the inner spacer 142 may not be removed in the etching process.

Referring to FIGS. 14A-14C, a gate dielectric layer 132 and a gate electrode 134 may be formed in a space from which the dummy gate insulating layer 132D and the dummy gate electrode 134D are removed. The gate electrode 134 may extend in the first horizontal direction D1. The gate dielectric layer 132 may be formed along surfaces of the device isolation layer 120, the channel layer 114, the gate spacer 140, and the inner spacer 142. The gate electrode 134 may be formed on the gate dielectric layer 132 and may surround the plurality of channel layers 114.

Referring back to FIGS. 2A-2D, a capping layer 170 may be formed to cover top surfaces of the gate electrode 134, the gate spacer 140, and the interlayer insulating layer 160. The capping layer 170 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

After the capping layer 170 is formed, a contact plug 180 penetrating the capping layer 170 and the interlayer insulating layer 160 may be formed. The contact plug 180 may be in contact with the top of the doped region 150 and the source/drain region 152. A silicide layer 182 may be formed under the contact plug 180. The silicide layer 182 may be disposed between the doped region 150 and the contact plug 180 and between the source/drain region 152 and the contact plug 180. The contact plug 180 may include W, Co, Cu, Al, Ti, Ta, TiN, TaN, or a combination thereof. The silicide layer 182 may include a material in which a silicon material is applied to portion of the contact plug 180.

A contact insulating layer 184, a via V, and interconnects L1, L2, L3, L4, L5, L6, and L may be formed on the capping layer 170. The contact insulating layer 184 may be disposed on the capping layer 170. The via V and the interconnects L1, L2, L3, L4, L5, L6, and L may pass through the contact insulating layer 184. In an example embodiment, each via V and the interconnects L1, L2, L3, L4, L5, L6, and L may be integrally formed. The contact insulating layer 184 may include silicon oxide. The vias V and the interconnects L1, L2, L3, L4, L5, L6, and L may include W, Co, Cu, Al, or a combination thereof.

While embodiments of inventive concepts have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of inventive concepts and without changing features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense and not for purposes of limitation.

According to example embodiments of inventive concepts, a resistance device with a surrounding gate structure may be implemented. 

What is clamed is:
 1. A method of manufacturing a semiconductor device comprising: forming a stack including a plurality of alternately stacked sacrificial layers and a plurality of channel layers on a resistor region and a transistor region of a substrate, the resistor region including an active region in an N well region; forming, in the resistor region, a first trench in an upper portion of the substrate and forming a first device isolation layer in the first trench; forming, in the transistor region, a second trench in the upper portion of the substrate and forming a second device isolation layer in the second trench; forming, in the resistor region, a third trench in the upper portion of the substrate and forming a buried insulating layer in the third trench, the buried insulating layer dividing the active region into a first active region and a second active region extending in a first horizontal direction; forming, in the resistor region, first dummy gate structures extending in a second horizontal direction crossing the first horizontal direction on the stack, each of the first dummy gate structures including a first dummy gate electrode and first gate spacers on side surfaces of the first dummy gate electrode; forming, in the transistor region, a second dummy gate structure extending in the second horizontal direction on the stack, the second dummy gate structure including a second dummy gate electrode and second gate spacers on side surfaces of the second dummy gate electrode; forming, in the resistor region, a first doped region and a second doped region each disposed on side surfaces of the first dummy gate structures on the first active region and the second active region; forming, in the transistor region, a source/drain region on side surfaces of the second dummy gate structure; removing the first dummy gate electrodes and forming first gate electrodes in a space where the first dummy gate electrodes are removed; and removing the second dummy gate electrode and forming a second gate electrode in a space where the second dummy gate electrode is removed, wherein the first doped region and the second doped region is in contact with the N well region and including n impurities.
 2. The method of claim 1, further comprising forming a plurality of contact plugs in contact with upper surfaces of the first doped region and the second doped region.
 3. The method of claim 2, wherein the plurality of contact plugs extends along the second horizontal direction and has a bar shape.
 4. The method of claim 1, wherein the N well region surrounds a lower surface of the buried insulating layer.
 5. The method of claim 1, wherein the first doped region and the second doped region are connected to at least one of the plurality of channel layers.
 6. The method of claim 1, wherein the first doped region is electrically connected with the second doped region through the first active region, the N well region, and the second active region.
 7. The method of claim 1, further comprising, before removing the first dummy gate electrodes and the second dummy gate electrode, forming a interlayer insulating layer covering the first device isolation layer, the second device isolation layer, the buried insulating layer, the first doped region, the second doped region and the source/drain region.
 8. The method of claim 1, wherein the plurality of channel layers is spaced apart from each other in a vertical direction.
 9. The method of claim 1, further comprising, before forming the first gate electrodes and the second gate electrode, removing the plurality of sacrificial layers, and wherein the first gate electrodes and the second gate electrode surround the plurality of channel layers.
 10. The method of claim 1, wherein doping concentrations of the first doped region and the second doped region are higher than a doping concentration of the N well region.
 11. The method of claim 1, wherein a depth of the buried insulating layer is greater than a depth of at least one of the first device isolation layer and second device isolation layer.
 12. The method of claim 1, wherein the first doped region and the second doped region are semiconductor layers epitaxially grown from the first active region and second active region, respectively.
 13. The method of claim 1, wherein the source/drain region has a conductivity type different from a conductive type of the active region.
 14. The method of claim 1, further comprising, before forming the first doped region and the second doped region, forming inner spacers on lower surfaces of the plurality of channel layers.
 15. The method of claim 14, wherein side surfaces of the first doped region and the second doped region are in contact with at least one of the inner spacers.
 16. The method of claim 1, wherein each of the first gate electrodes includes a first upper electrode on the plurality of channel layers and a first lower electrode below the first upper electrode and separated by the plurality of channel layers.
 17. A method of manufacturing a resistor comprising: forming a stack including a plurality of alternately stacked sacrificial layers and a plurality of channel layers on a substrate, the substrate including an active region in an N well region; forming a first trench in an upper portion of the substrate and forming a device isolation layer in the first trench; forming a second trench in the upper portion of the substrate and forming a buried insulating layer in the second trench, the buried insulating layer dividing the active region into a first active region and a second active region extending in a first horizontal direction; forming dummy gate structures extending in a second horizontal direction crossing the first horizontal direction on the stack, each of the dummy gate structures including dummy gate electrodes and gate spacers on side surfaces of the dummy gate electrodes; forming inner spacers on lower surfaces of the plurality of channel layers; forming a first doped region and second doped region each disposed on side surfaces of the dummy gate structures and on the first active region and the second active region; removing the dummy gate electrodes and forming gate electrodes in a space where the dummy gate electrodes are removed; and forming a plurality of contact plugs in contact with upper surfaces of the first doped region and the second doped region, wherein the first doped region and the second doped region is in contact with the N well region and including n impurities.
 18. The method of claim 17, wherein the buried insulating layer extending along the second horizontal direction.
 19. The method of claim 17, wherein the first active region and the second active region are spaced apart from each other in the first horizontal direction.
 20. The method of claim 17, wherein the first doped region is electrically connected with the second doped region through the first active region, the N well region, and the second active region. 